 Virtuoso UltraSim Full-chip Simulator vMMSIM培訓(xùn) |
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班級規(guī)模及環(huán)境 |
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上課時間和地點(diǎn) |
上課地點(diǎn)：【上海】：同濟(jì)大學(xué)(滬西)/新城金郡商務(wù)樓(11號線白銀路站) 【深圳分部】：電影大廈(地鐵一號線大劇院站)/深圳大學(xué)成教院
【北京分部】：北京中山學(xué)院/福鑫大樓 【南京分部】：金港大廈(和燕路) 【武漢分部】：佳源大廈（高新二路）
【成都分部】：領(lǐng)館區(qū)1號（中和大道）
最近開課時間(周末班/連續(xù)班/晚班）：Virtuoso UltraSim Full-chip Simulator vMMSIM培訓(xùn)：2025年12月15日..以服務(wù)質(zhì)量為生命....共贏、共創(chuàng)....資深工程師授課.....直播、現(xiàn)場培訓(xùn)皆可....用心服務(wù).......... |
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學(xué)時 |
◆課時： 一個月
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Virtuoso UltraSim Full-chip Simulator vMMSIM培訓(xùn)
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Course Description
In this course, you run FastSPICE simulation on large, complex, mixed-signal designs using the Virtuoso? UltraSim Full-chip Simulator. You explore the capabilities, methods, and modes of the simulator. You apply a variety of configurations that exploit the simulator's commands and options. You gain experience with hierarchical simulations, simulations of individual blocks, aged simulations, and EMIR analysis.
Learning Objectives
After completing this course, you will be able to:
- Simulate complex mixed-signal circuits quickly, using the FastSPICE simulator and Virtuoso UltraSim Full-chip Simulator
- Adjust the simulator's option settings to produce the proper tradeoff between accuracy and speed
- Construct probes and measures for reporting circuit performance during simulation
- Examine postprocessing measurement
- Verify the circuit performance and identify the potential failure modes by running advanced analysis, including static and dynamic checks
- Run hierarchical top-level simulations for prelayout, combining transistor-level schematics with structural Verilog? HDL, behavioral Verilog-A models, or behavioral Verilog HDL models, digital stimulus (.vec, .vcd) files and postlayout simulation with adjustable parasitic reduction
- Analyze the potential IR drop and electromigration (EM) problems in the layout by using Power IR/EM option and netlist-based EMIR
- Effectively use the integration of FastSPICE simulation in the Analog Design Environment to improve silicon accuracy and time-to-market
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